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MISO/HSD, and SS /HSA. The functions used in the SPI-compatible
interface are SCLK, MOSI, MISO, and SS . The serial clock for
read/ write bit. Because this is a read operation, it must be set to 1;
ADE7816
I 2 C Read Operation
The read operation, using the I 2 C interface of the ADE7816 , is
accomplished in two stages. The first stage sets the pointer to
the address of the register; the second stage reads the contents
The first stage is initiated when the master generates a start con-
dition. It consists of one byte, representing the address of the
ADE7816 acknowledges every byte received. The address byte is
similar to the address byte of a write operation and is equal to 0x70
(see the I 2 C Write Operation section for details). After the last
byte of the register address is sent and acknowledged by the
a new start condition, followed by an address byte. The most
significant seven bits of this address byte constitute the address of
the ADE7816 , which is 0111000b. Bit 0 of the address byte is a
E
A A
therefore, the first byte of the read operation is 0x71. After this byte
is received, the ADE7816 generates an acknowledge. Then the
Data Sheet
SPI-Compatible Interface
The ADE7816 SPI is always a slave of the communication and
consists of four pins (with dual functions): SCLK/SCL, MOSI/SDA,
E
A A
E
A A
a data transfer is applied at the SCLK logic input. This logic input
has a Schmitt trigger input structure that allows the use of slow
rising (and falling) clock edges. All data transfer operations
synchronize to the serial clock. Data shifts into the ADE7816
at the MOSI logic input on the falling edge of SCLK, and the
ADE7816 samples it on the rising edge of SCLK. Data shifts out
of the ADE7816 at the MISO logic output on a falling edge of
SCLK and can be sampled by the master device on the raising
edge of SCLK. The most significant bit of the word is shifted in
and out first. The maximum serial clock frequency that is
supported by this interface is 2.5 MHz. MISO stays in high
SPI and a master device containing a SPI interface.
ADE7816 sends the value of the register, and, after every eight bits
are received, the master generates an acknowledge. All the bytes
are sent with the most significant bit first. Registers can be 8, 16,
or 32 bits. After the last bit of the register is received, the master
does not acknowledge the transfer but, instead, generates a stop
ADE7816
MOSI/SDA
MISO/HSD
SCLK/SCL
SS/HSA
SPI DEVICE
MOSI
MISO
SCK
SS
condition.
Figure 38. Connecting the ADE7816 SPI with a SPI Device
15
8
7
0
31
16
15
8
7
0
7
0
S 0 1 1 1 0 0 0 0
S
SLAVE ADDRESS
A MS 8 BITS OF A LS 8 BITS OF A
C REGISTER ADDRESS C REGISTER ADDRESS C
K K K
BYTE 3 (MS)
OF REGISTER
A A A
C BYTE 2 OF REGISTER C BYTE 1 OF REGISTER C
K K K
BYTE 0 (LS) OF
REGISTER
A
C
K
ACKNOWLEDGE
GENERATED BY
ADE7816
Figure 39. I 2 C Write Operation of a 32-Bit Register
15
8
7
0
S 0 1 1 1 0 0 0 0
SLAVE ADDRESS
A MSB 8 BITS OF
C REGISTER ADDRESS
K
A LSB 8 BITS OF
C REGISTER ADDRESS
K
A
C
K
ACKNOWLEDGE
GENERATED BY
ADE7816
ACKNOWLEDGE
GENERATED BY
MASTER
N
O
31
A
16 C 15
K
A
8 C
K
7
A
0 C
K
7
A
C
0 K
S
0
1
1
1
0
0
0 1
S
SLAVE ADDRESS
A
C
K
BYTE 3 (MSB)
OF REGISTER
BYTE 2 OF
REGISTER
BYTE 1 OF
REGISTER
BYTE 0 (LSB)
OF REGISTER
ACKNOWLEDGE
GENERATED BY
ADE7816
Figure 40. I 2 C Read Operation of a 32-Bit Register
Rev. A | Page 32 of 48
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